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MSS
2005
IEEE
62views Hardware» more  MSS 2005»
14 years 3 months ago
Predictive Reduction of Power and Latency (PuRPLe)
Increasing efforts have been aimed towards the management of power as a critical system resource, and the disk can consume approximately a third of the power required for a typica...
Matthew Craven, Ahmed Amer
ISCA
2010
IEEE
214views Hardware» more  ISCA 2010»
14 years 3 months ago
Re-architecting DRAM memory systems with monolithically integrated silicon photonics
The performance of future manycore processors will only scale with the number of integrated cores if there is a corresponding increase in memory bandwidth. Projected scaling of el...
Scott Beamer, Chen Sun, Yong-Jin Kwon, Ajay Joshi,...
PASTE
2010
ACM
14 years 3 months ago
Opportunities for concurrent dynamic analysis with explicit inter-core communication
Multicore is now the dominant processor trend, and the number of cores is rapidly increasing. The paradigm shift to multicore forces the redesign of the software stack, which incl...
Jungwoo Ha, Stephen P. Crago
NDSS
2000
IEEE
14 years 2 months ago
Accountability and Control of Process Creation in Metasystems
The distinguishing feature of a metasystem is middleware that facilitates viewing a collection of large, distributed, heterogeneous resources as a single virtual machine, where ea...
Marty Humphrey, Frederick Knabe, Adam Ferrari, And...
SIGGRAPH
2000
ACM
14 years 2 months ago
The WarpEngine: an architecture for the post-polygonal age
We present the WarpEngine, an architecture designed for realtime image-based rendering of natural scenes from arbitrary viewpoints. The modeling primitives are real-world images w...
Voicu Popescu, John G. Eyles, Anselmo Lastra, Josh...