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HPCA
1999
IEEE
14 years 6 days ago
Instruction Recycling on a Multiple-Path Processor
Processors that can simultaneously execute multiple paths of execution will only exacerbate the fetch bandwidth problem already plaguing conventional processors. On a multiple-pat...
Steven Wallace, Dean M. Tullsen, Brad Calder
ASPLOS
2008
ACM
13 years 10 months ago
Accurate branch prediction for short threads
Multi-core processors, with low communication costs and high availability of execution cores, will increase the use of execution and compilation models that use short threads to e...
Bumyong Choi, Leo Porter, Dean M. Tullsen
HPCA
2008
IEEE
14 years 8 months ago
Power-Efficient DRAM Speculation
Power-Efficient DRAM Speculation (PEDS) is a power optimization targeted at broadcast-based sharedmemory multiprocessor systems that speculatively access DRAM in parallel with the...
Nidhi Aggarwal, Jason F. Cantin, Mikko H. Lipasti,...
CAINE
2003
13 years 9 months ago
An Issue Logic for Superscalar Microprocessors
In order to enhance the computer performance, nowadays microprocessors use Superscalar architecture. But the Superscalar architecture is unable to enhance the performance effectiv...
Feng-Jiann Shiao, Jong-Jiann Shieh
ISCA
2002
IEEE
104views Hardware» more  ISCA 2002»
13 years 7 months ago
Speculative Dynamic Vectorization
Traditional vector architectures have shown to be very effective for regular codes where the compiler can detect data-level parallelism. However, this SIMD parallelism is also pre...
Alex Pajuelo, Antonio González, Mateo Valer...