Abstract: The time-triggered System-on-a-Chip (SoC) architecture provides a generic multicore system platform for a family of composable and dependable giga-scale SoCs. It supports...
Roman Obermaisser, Hermann Kopetz, Christian El Sa...
In this paper, we formulate the array robustness theorems (ARTs) for efficient computation and communication on faulty arrays. No hardware redundancy is required and no assumptio...
Statement and AbstractProblem Statement and AbstractProblem Statement and AbstractProblem Statement and Abstract The U.S. Navy currently bases the majority of our contact managemen...
In this paper, we propose a general cross-layer optimization framework in which we explicitly consider both the heterogeneous and dynamically changing characteristics of delay-sens...
The existence of good probabilistic models for the job arrival process and the delay components introduced at different stages of job processing in a Grid environment is important ...