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IESS
2007
Springer
120views Hardware» more  IESS 2007»
14 years 1 months ago
Error Containment in the Time-Triggered System-On-a-Chip Architecture
Abstract: The time-triggered System-on-a-Chip (SoC) architecture provides a generic multicore system platform for a family of composable and dependable giga-scale SoCs. It supports...
Roman Obermaisser, Hermann Kopetz, Christian El Sa...
ICPP
2002
IEEE
14 years 11 days ago
ART: Robustness of Meshes and Tori for Parallel and Distributed Computation
In this paper, we formulate the array robustness theorems (ARTs) for efficient computation and communication on faulty arrays. No hardware redundancy is required and no assumptio...
Chi-Hsiang Yeh, Behrooz Parhami
SIGADA
2001
Springer
13 years 12 months ago
Electronic maneuvering board and dead reckoning tracer decision aid for the officer of the deck
Statement and AbstractProblem Statement and AbstractProblem Statement and AbstractProblem Statement and Abstract The U.S. Navy currently bases the majority of our contact managemen...
Kenneth L. Ehresman, Joey L. Frantzen
CORR
2008
Springer
173views Education» more  CORR 2008»
13 years 7 months ago
Decomposition Principles and Online Learning in Cross-Layer Optimization for Delay-Sensitive Applications
In this paper, we propose a general cross-layer optimization framework in which we explicitly consider both the heterogeneous and dynamically changing characteristics of delay-sens...
Fangwen Fu, Mihaela van der Schaar
GRID
2008
Springer
13 years 7 months ago
Statistical Analysis and Modeling of Jobs in a Grid Environment
The existence of good probabilistic models for the job arrival process and the delay components introduced at different stages of job processing in a Grid environment is important ...
Kostas Christodoulopoulos, Vasileios Gkamas, Emman...