244 search results - page 15 / 49 » Data partitioning on chip multiprocessors |
DSN
2011
IEEE
12 years 9 months ago
2011
IEEE
—Aggressive technology scaling causes chip multiprocessors increasingly error-prone. Core-level faulttolerant approaches bind two cores to implement redundant execution and error...
MICRO
2007
IEEE
14 years 4 months ago
2007
IEEE
DRAM memory is a major resource shared among cores in a chip multiprocessor (CMP) system. Memory requests from different threads can interfere with each other. Existing memory acc...
HIPEAC
2009
Springer
14 years 4 months ago
2009
Springer
Process variations, which lead to timing and power variations across identically-designed components, have been identified as one of the key future design challenges by the semico...
CF
2009
ACM
14 years 4 months ago
2009
ACM
Chip Multiprocessor (CMP) memory systems suffer from the effects of destructive thread interference. This interference reduces performance predictability because it depends heavil...
DSN
2007
IEEE
14 years 4 months ago
2007
IEEE
Aggressive CMOS scaling will make future chip multiprocessors (CMPs) increasingly susceptible to transient faults, hard errors, manufacturing defects, and process variations. Exis...