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» Data-Flow Frameworks for Worst-Case Execution Time Analysis
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CASES
2004
ACM
14 years 1 months ago
High-level power analysis for on-chip networks
As on-chip networks become prevalent in multiprocessor systemson-a-chip and multi-core processors, they will be an integral part of the design flow of such systems. With power in...
Noel Eisley, Li-Shiuan Peh
SIGMOD
2012
ACM
220views Database» more  SIGMOD 2012»
11 years 10 months ago
GUPT: privacy preserving data analysis made easy
It is often highly valuable for organizations to have their data analyzed by external agents. However, any program that computes on potentially sensitive data risks leaking inform...
Prashanth Mohan, Abhradeep Thakurta, Elaine Shi, D...
PADS
2005
ACM
14 years 1 months ago
Concurrent Replication of Parallel and Distributed Simulations
Parallel and distributed simulations enable the analysis of complex systems by concurrently exploiting the aggregate computation power and memory of clusters of execution units. I...
Luciano Bononi, Michele Bracuto, Gabriele D'Angelo...
RTSS
2006
IEEE
14 years 1 months ago
Run-Time Services for Hybrid CPU/FPGA Systems on Chip
Modern FPGA devices, which include (multiple) processor core(s) as diffused IP on the silicon die, provide an excellent platform for developing custom multiprocessor systems-on-pr...
Jason Agron, Wesley Peck, Erik Anderson, David L. ...
ICLP
2010
Springer
13 years 5 months ago
A Framework for Verification and Debugging of Resource Usage Properties: Resource Usage Verification
We present a framework for (static) verification of general resource usage program properties. The framework extends the criteria of correctness as the conformance of a program to ...
Pedro López-García, Luthfi Darmawan,...