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» Datapath Scheduling using Dynamic Frequency Clocking
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IPPS
2006
IEEE
14 years 1 months ago
Analysis of checksum-based execution schemes for pipelined processors
The performance requirements for contemporary microprocessors are increasing as rapidly as their number of applications grows. By accelerating the clock, performance can be gained...
Bernhard Fechner
RTAS
2007
IEEE
14 years 1 months ago
Reliability-Aware Energy Management for Periodic Real-Time Tasks
The prominent energy management technique in real-time embedded systems, Dynamic Voltage and Frequency Scaling (DVFS), was recently shown to have direct and adverse effects on sys...
Dakai Zhu, Hakan Aydin
ISCA
1993
IEEE
125views Hardware» more  ISCA 1993»
13 years 11 months ago
Evaluation of Mechanisms for Fine-Grained Parallel Programs in the J-Machine and the CM-5
er uses an abstract machine approach to compare the mechanisms of two parallel machines: the J-Machine and the CM-5. High-level parallel programs are translated by a single optimi...
Ellen Spertus, Seth Copen Goldstein, Klaus E. Scha...
ISVLSI
2008
IEEE
143views VLSI» more  ISVLSI 2008»
14 years 1 months ago
BTB Access Filtering: A Low Energy and High Performance Design
Powerful branch predictors along with a large branch target buffer (BTB) are employed in superscalar processors for instruction-level parallelism exploitation. However, the large ...
Shuai Wang, Jie Hu, Sotirios G. Ziavras
PLDI
2011
ACM
12 years 10 months ago
Caisson: a hardware description language for secure information flow
Information flow is an important security property that must be incorporated from the ground up, including at hardware design time, to provide a formal basis for a system’s roo...
Xun Li 0001, Mohit Tiwari, Jason Oberg, Vineeth Ka...