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DATE
2006
IEEE
176views Hardware» more  DATE 2006»
15 years 10 months ago
Low power synthesis of dynamic logic circuits using fine-grained clock gating
— Clock power consumes a significant fraction of total power dissipation in high speed precharge/evaluate logic styles. In this paper, we present a novel low-cost design methodol...
Nilanjan Banerjee, Kaushik Roy, Hamid Mahmoodi-Mei...
DATE
2006
IEEE
108views Hardware» more  DATE 2006»
15 years 10 months ago
Automatic march tests generations for static linked faults in SRAMs
Static Linked Faults are considered an interesting class of memory faults. Their capability of influencing the behavior of other faults causes the hiding of the fault effect and m...
Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Gi...
DATE
2006
IEEE
95views Hardware» more  DATE 2006»
15 years 10 months ago
An effective technique for minimizing the cost of processor software-based diagnosis in SoCs
The ever increasing usage of microprocessor devices is sustained by a high volume production that in turn requires a high production yield, backed by a controlled process. Fault d...
Paolo Bernardi, Ernesto Sánchez, Massimilia...
DATE
2006
IEEE
352views Hardware» more  DATE 2006»
15 years 10 months ago
Fast-prototyping using the BTnode platform
The BTnode platform is a versatile and flexible platform for functional prototyping of ad hoc and sensor networks. Based on an Atmel microcontroller, a Bluetooth radio and a low-...
Jan Beutel
DATE
2006
IEEE
86views Hardware» more  DATE 2006»
15 years 10 months ago
Synthesis of system verilog assertions
In recent years, Assertion-Based Verification is being widely accepted as a key technology in the pre-silicon validation of system-on-chip(SOC) designs. The System Verilog langua...
Sayantan Das, Rizi Mohanty, Pallab Dasgupta, P. P....