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2003
IEEE
87views Hardware» more  DATE 2003»
15 years 9 months ago
A Proposal for Transaction-Level Verification with Component Wrapper Language
We propose a new approach to accelerate transaction level verification by raising the productivity of the verification suites including test patterns, protocol checker, and simula...
Koji Ara, Kei Suzuki
DATE
2003
IEEE
151views Hardware» more  DATE 2003»
15 years 9 months ago
Analysis and White-Box Modeling of Weakly Nonlinear Time-Varying Circuits
The architectural study of wireless communication systems typically requires simulations with high-level models for different analog and RF blocks. Among these blocks, frequency-t...
Petr Dobrovolný, Gerd Vandersteen, Piet Wam...
DATE
2003
IEEE
96views Hardware» more  DATE 2003»
15 years 9 months ago
Test Data Compression: The System Integrator's Perspective
Test data compression (TDC) is a promising low-cost methodology for System-on-a-Chip (SOC) test. This is due to the fact that it can reduce not only the volume of test data but al...
Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola N...
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DATE
2003
IEEE
130views Hardware» more  DATE 2003»
15 years 9 months ago
A Technique for High Ratio LZW Compression
Reduction of both the test suite size and the download time of test vectors is important in today's System-On-a-Chip designs. In this paper, a method for compressing the scan...
Michael J. Knieser, Francis G. Wolff, Christos A. ...
DATE
2003
IEEE
103views Hardware» more  DATE 2003»
15 years 9 months ago
Verification of the RF Subsystem within Wireless LAN System Level Simulation
Today’s mobile communication systems use sophisticated signal processing to achieve high transmission rates. Therefore a high complexity in the digital system part as well as ve...
Uwe Knöchel, Thomas Markwirth, Jürgen Ha...