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DATE
2006
IEEE
133views Hardware» more  DATE 2006»
15 years 10 months ago
Automatic generation of operation tables for fast exploration of bypasses in embedded processors
Customizing the bypasses in an embedded processor uncovers valuable trade-offs between the power, performance and the cost of the processor. Meaningful exploration of bypasses re...
Sanghyun Park, Eugene Earlie, Aviral Shrivastava, ...
DATE
2006
IEEE
114views Hardware» more  DATE 2006»
15 years 10 months ago
An efficient static algorithm for computing the soft error rates of combinational circuits
Soft errors have emerged as an important reliability challenge for nanoscale VLSI designs. In this paper, we present a fast and efficient soft error rate (SER) computation algorit...
Rajeev R. Rao, Kaviraj Chopra, David Blaauw, Denni...
DATE
2006
IEEE
153views Hardware» more  DATE 2006»
15 years 10 months ago
Analyzing timing uncertainty in mesh-based clock architectures
Mesh architectures are used to distribute critical global signals on a chip, such as clock and power/ground. Redundancy created by mesh loops smooths out undesirable variations be...
Subodh M. Reddy, Gustavo R. Wilke, Rajeev Murgai
DATE
2006
IEEE
113views Hardware» more  DATE 2006»
15 years 10 months ago
An interprocedural code optimization technique for network processors using hardware multi-threading support
Sophisticated C compiler support for network processors (NPUs) is required to improve their usability and consequently, their acceptance in system design. Nonetheless, high-level ...
Hanno Scharwächter, Manuel Hohenauer, Rainer ...
DATE
2006
IEEE
104views Hardware» more  DATE 2006»
15 years 10 months ago
Equivalence verification of arithmetic datapaths with multiple word-length operands
Abstract: This paper addresses the problem of equivalence verification of RTL descriptions that implement arithmetic computations (add, mult, shift) over bitvectors that have di...
Namrata Shekhar, Priyank Kalla, Florian Enescu