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114
Voted
DFT
2008
IEEE
86views VLSI» more  DFT 2008»
15 years 10 months ago
Enhancing Silicon Debug via Periodic Monitoring
Scan-based debug methods give high observability of internal signals, however, they require halting the system to scan out responses from the circuit-under-debug (CUD). This is ti...
Joon-Sung Yang, Nur A. Touba
114
Voted
FMCAD
2009
Springer
15 years 10 months ago
Scaling VLSI design debugging with interpolation
—Given an erroneous design, functional verification returns an error trace exhibiting a mismatch between the specification and the implementation of a design. Automated design ...
Brian Keng, Andreas G. Veneris
99
Voted
DATE
2005
IEEE
197views Hardware» more  DATE 2005»
15 years 9 months ago
picoArray Technology: The Tool's Story
This paper briefly describes the picoArrayTM architecture, and in particular the deterministic internal communication fabric. The methods that have been developed for debugging a...
Andrew Duller, Daniel Towner, Gajinder Panesar, Al...
123
Voted
SOSP
2003
ACM
16 years 16 days ago
Performance debugging for distributed systems of black boxes
Many interesting large-scale systems are distributed systems of multiple communicating components. Such systems can be very hard to debug, especially when they exhibit poor perfor...
Marcos Kawazoe Aguilera, Jeffrey C. Mogul, Janet L...
127
Voted
DAGSTUHL
2006
15 years 5 months ago
A Petri Net Approach to Verify and Debug Simulation Models
Verification and Simulation share many issues, one is that simulation models require validation and verification. In the context of simulation, verification is understood as the ta...
Peter Kemper, Carsten Tepper