1545 search results - page 189 / 309 » Defeasible Description Logics |
JELIA
2004
Springer
14 years 1 months ago
2004
Springer
We briefly overview the most recent improvements we have incorporated to the existent implementations of the TAS methodology, the simplified ∆-tree representation of formulas i...
CSREAESA
2003
13 years 9 months ago
2003
Most so-called “adiabatic” digital logic circuit families reported in the low-power design literature are actually not truly adiabatic, in that they do not satisfy the general...
TODAES
2002
13 years 7 months ago
2002
ct Cross-coupled noise analysis has become a critical concern in today's VLSI designs. Typically, noise analysis makes an assumption that all aggressing nets can simultaneousl...
LOGCOM
2007
13 years 8 months ago
2007
Categorisation of objects into classes is currently supported by (at least) two ‘orthogonal’ methods. In logic-based approaches, classifications are defined through ontologi...
ICCAD
2002
IEEE
14 years 5 months ago
2002
IEEE
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...