38 search results - page 1 / 8 » Delay-Insensitive Ternary Logic |
CDES
2009
13 years 12 months ago
2009
This paper develops a delay-insensitive (DI) digital design paradigm that utilizes ternary logic as an alternative to dual-rail logic for encoding the DATA and NULL states. This ne...
ASYNC
1997
IEEE
14 years 3 months ago
1997
IEEE
The realisation of Delay-Insensitive (DI) asynchronous circuits with a CMOS ternary logic is described in this paper. The main advantage of temary logic is the easy realisation of...
ISMVL
1997
IEEE
14 years 3 months ago
1997
IEEE
This paper shows how the application of a CMOS ternary logic is useful in the realisation of Delay Insensitive (01)asynchronous circuits. It is shown that fully DIasynchronous cir...
ASYNC
1998
IEEE
14 years 3 months ago
1998
IEEE
ASYNC
2002
IEEE
14 years 3 months ago
2002
IEEE
Wire and gate delays are accounted to have equal, or nearly equal, effect on circuit behavior in modern design techniques. This paper introduces a new approach to verify circuits ...