Delay-Insensitive Ternary Logic

This paper develops a delay-insensitive (DI) digital design paradigm that utilizes ternary logic as an alternative to dual-rail logic for encoding the DATA and NULL states. This new Delay-Insensitive Ternary Logic (DITL) paradigm is compared with other DI paradigms, such as Pre-Charge HalfBuffers (PCHB) and NULL Convention Logic (NCL), showing that DITL significantly outperforms PCHB and NCL in terms of energy consumption, and is also more area efficient than NCL. Utilizing the DITL paradigm for designing secure hardware applications is then discussed. Keywords-digital logic; asynchronous; delay-insensitive; clockless; ternary; PCHB; NCL; DITL; secure hardware

• Type: Conference
• Year: 2009
• Where: CDES
• Authors: Ravi Sankar Parameswaran Nair, Scott C. Smith, Jia Di
• Keywords: CDES 2007, CDES 2009, Delay-Insensitive Ternary Logic, Null Convention Logic, Ternary Logic