822 search results - page 147 / 165 » Descendants in Increasing Trees |
DAC
2003
ACM
14 years 8 months ago
2003
ACM
We present in this paper a multilevel floorplanning/placement framework based on the B*-tree representation, called MB*-tree, to handle the floorplanning and packing for large-sca...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
As technology advances into the nanometer territory, the interconnect delay has become a first-order effect on chip performance. To handle this effect, the X-architecture has been...
WWW
2005
ACM
14 years 8 months ago
2005
ACM
While the idea that querying mechanisms for complex relationships (otherwise known as Semantic Associations) should be integral to Semantic Web search technologies has recently ga...
PPOPP
2009
ACM
14 years 8 months ago
2009
ACM
Due to power wall, memory wall, and ILP wall, we are facing the end of ever increasing single-threaded performance. For this reason, multicore and manycore processors are arising ...
HPCA
2009
IEEE
14 years 8 months ago
2009
IEEE
Network-on-Chips (NoCs) are quite latency sensitive, since their communication latency strongly affects the application performance on recent many-core architectures. To reduce th...