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VLSID
1999
IEEE
122views VLSI» more  VLSID 1999»
14 years 3 months ago
Formal Verification of an ARM Processor
This paper presents a detailed description of the application of a formal verification methodology to an ARM processor. The processor, a hybrid between the ARM7 and the StrongARM ...
Vishnu A. Patankar, Alok Jain, Randal E. Bryant
RSP
1998
IEEE
126views Control Systems» more  RSP 1998»
14 years 3 months ago
Testing Prototypes Validity to Enhance Code Reuse
The complexity of distributed systems is a problem when designers want to evaluate their safety and liveness. Often, they are built by integration of existing components with newl...
Didier Buchs, A. Diagne, Fabrice Kordon
ISMVL
1997
IEEE
134views Hardware» more  ISMVL 1997»
14 years 3 months ago
Functional Decomposition of MVL Functions Using Multi-Valued Decision Diagrams
In this paper, the minimization of incompletely specified multi-valued functions using functional decomposition is discussed. From the aspect of machine learning, learning sample...
Craig M. Files, Rolf Drechsler, Marek A. Perkowski
VL
1996
IEEE
123views Visual Languages» more  VL 1996»
14 years 2 months ago
GenEd - An Editor with Generic Semantics for Formal Reasoning about Visual Notations
We describe the object-oriented editor GenEd supporting the design of specifications for visual notations. Prominent features of GenEd are (1) it is generic, i.e. domain-specific ...
Volker Haarslev, Michael Wessel
DAC
1994
ACM
14 years 2 months ago
Functional Test Generation for FSMs by Fault Extraction
Recent results indicate that functional test pattern generation (TPG) techniques may provide better defect coverages than do traditional logic-level techniques. Functional TPG alg...
Bapiraju Vinnakota, Jason Andrews