135 search results - page 18 / 27 » Design, layout and verification of an FPGA using automated t... |
ICFP
2009
ACM
14 years 8 months ago
2009
ACM
We present a new approach for constructing and verifying higherorder, imperative programs using the Coq proof assistant. We build on the past work on the Ynot system, which is bas...
DAC
2001
ACM
14 years 8 months ago
2001
ACM
roperty Verification by Abstraction Refinement with Formal, Simulation and Hybrid Engines Dong Wang , Pei-Hsin Ho , Jiang Long , James Kukula Yunshan Zhu , Tony Ma , Robert D...
FDL
2005
IEEE
14 years 1 months ago
2005
IEEE
In order to address the complexities of SoC design, rigorous development methods and automated tools are required. This paper presents an approach to formal verification using mod...
KDD
2003
ACM
14 years 8 months ago
2003
ACM
In today's industry, the design of software tests is mostly based on the testers' expertise, while test automation tools are limited to execution of pre-planned tests on...
DAC
2000
ACM
14 years 8 months ago
2000
ACM
We recently introduced symbolic timing simulation (STS) using data-dependent delays as a tool for verifying the timing of fullcustom transistor-level circuit designs, and for the ...