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ISCAS
2007
IEEE
123views Hardware» more  ISCAS 2007»
14 years 2 months ago
Evaluating Network-on-Chip for Homogeneous Embedded Multiprocessors in FPGAs
— This paper presents performance and area evaluation of a homogeneous multiprocessor communication system based on network-on-chip (NoC) in FPGA platforms. Two homogenous chip m...
Henrique C. Freitas, Dalton M. Colombo, Fernanda L...
CVIU
2010
267views more  CVIU 2010»
13 years 5 months ago
Accelerated hardware video object segmentation: From foreground detection to connected components labelling
This paper demonstrates the use of a single-chip FPGA for the segmentation of moving objects in a video sequence. The system maintains highly accurate background models, and integ...
Kofi Appiah, Andrew Hunter, Patrick Dickinson, Hon...
CAISE
2003
Springer
14 years 1 months ago
A Methodology for Multilevel Database Design
Abstract. In a Connected Society, the importance of database privacy and security increases considerably. Security must be considered as a fundamental requirement in Information Sy...
Eduardo Fernández-Medina, Mario Piattini
TVLSI
2008
164views more  TVLSI 2008»
13 years 7 months ago
Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication
The on-chip communication architecture is a major determinant of overall performance in complex System-on-Chip (SoC) designs. Since the communication requirements of SoC components...
Krishna Sekar, Kanishka Lahiri, Anand Raghunathan,...
IJCNN
2008
IEEE
14 years 2 months ago
Evolving a neural network using dyadic connections
—Since machine learning has become a tool to make more efficient design of sophisticated systems, we present in this paper a novel methodology to create powerful neural network ...
Andreas Huemer, Mario A. Góngora, David A. ...