3130 search results - page 180 / 626 » Design Correctness of Digital Systems |
126
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MICRO
2010
IEEE
15 years 2 months ago
2010
IEEE
We propose an architectural design methodology for designing formally verifiable cache coherence protocols, called Fractal Coherence. Properly designed to be fractal in behavior, t...
120
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SBCCI
2006
ACM
15 years 10 months ago
2006
ACM
This paper presents the design of asynchronous circuits on synchronous FPGAs and CPLDs. Different design styles have been investigated through the implementation of dual-rail full...
167
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CORR
2007
Springer
15 years 4 months ago
2007
Springer
This paper presents a methodology to efficiently explore the design space of communication adapters. In most digital signal processing (DSP) applications, the overall performance ...
156
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CASES
2005
ACM
15 years 6 months ago
2005
ACM
Instruction set customization accelerates the performance of applications by compressing the length of critical dependence paths and reducing the demands on processor resources. W...
154
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ICCAD
1995
IEEE
15 years 7 months ago
1995
IEEE
In this paper we investigate activity-driven clock trees to reduce the dynamic power consumption of synchronous digital CMOS circuits. Sections of an activity-driven clock tree ca...