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» Design For Testability Method for CML Digital Circuits
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DATE
2000
IEEE
110views Hardware» more  DATE 2000»
14 years 3 days ago
Stochastic Modeling and Performance Evaluation for Digital Clock and Data Recovery Circuits
Clock and data recovery circuits are essential components in communication systems. They directly influence the bit-error-rate performance of communication links. It is desirable...
Alper Demir, Peter Feldmann
CEC
2009
IEEE
14 years 2 months ago
Gate-level optimization of polymorphic circuits using Cartesian Genetic Programming
— Polymorphic digital circuits contain ordinary and polymorphic gates. In the past, Cartesian Genetic Programming (CGP) has been applied to synthesize polymorphic circuits at the...
Zbysek Gajda, Lukás Sekanina
KES
2008
Springer
13 years 7 months ago
Instruction-based development: From evolution to generic structures of digital circuits
Evolutionary techniques provide powerful tools to design novel solutions for hard problems in different areas. However, the problem of scale (i.e. how to create a large, complex s...
Michal Bidlo, Jaroslav Skarvada
APIN
2002
121views more  APIN 2002»
13 years 7 months ago
Applying Learning by Examples for Digital Design Automation
This paper describes a new learning by example mechanism and its application for digital circuit design automation. This mechanism uses finite state machines to represent the infer...
Ben Choi
ICASSP
2011
IEEE
12 years 11 months ago
Reduced-hardware digital filter design via joint quantization and multiple constant multiplication optimization
The focus of this paper is to provide a framework for the joint optimization of both the coefficient quantization and multiple constant multiplication (MCM) problems. It is known...
Matthew B. Gately, Mark B. Yeary, Choon Yik Tang