Sciweavers

124 search results - page 1 / 25
» Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Digi...
Sort
View
DATE
2008
IEEE
126views Hardware» more  DATE 2008»
14 years 1 months ago
Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits
Metallic Carbon Nanotubes (CNTs) create source-drain shorts in Carbon Nanotube Field Effect Transistors (CNFETs), causing excessive leakage, degraded noise margin and delay variat...
Jie Zhang, Nishant Patil, Subhasish Mitra
PARLE
1987
13 years 10 months ago
Emulating Digital Logic using Transputer Networks (very High Parallelism = Simplicity = Performance)
Modern VLSI technology has changed the economic rules by which the balance between processing power, memory and communications is decided in computing systems. This will have a pr...
Peter H. Welch
DAGSTUHL
2007
13 years 8 months ago
Parallelism through Digital Circuit Design
Abstract. Two ways to exploit chips with a very large number of transistors are multicore processors and programmable logic chips. Some data parallel algorithms can be executed eï¬...
John O'Donnell
TVLSI
2002
366views more  TVLSI 2002»
13 years 6 months ago
Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits
Gate diffusion input (GDI)--a new technique of low-power digital combinatorial circuit design--is described. This technique allows reducing power consumption, propagation delay, an...
Arkadiy Morgenshtein, Alexander Fish, Israel A. Wa...
EVOW
2008
Springer
13 years 8 months ago
Analysis of Reconfigurable Logic Blocks for Evolvable Digital Architectures
Abstract. In this paper we propose three small instances of a reconfigurable circuit and analyze their properties using the brute force method and evolutionary algorithm. Although ...
Lukás Sekanina, Petr Mikusek