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ICES
2000
Springer
140views Hardware» more  ICES 2000»
13 years 11 months ago
Evolving Cellular Automata for Self-Testing Hardware
Testing is a key issue in the design and production of digital circuits: the adoption of BIST (Built-In Self-Test) techniques is increasingly popular, but requires efficient algori...
Fulvio Corno, Matteo Sonza Reorda, Giovanni Squill...
VLSID
2009
IEEE
155views VLSI» more  VLSID 2009»
14 years 8 months ago
Unified Challenges in Nano-CMOS High-Level Synthesis
: The challenges in nano-CMOS circuit design include the following: variability, leakage, power, thermals, reliability, and yield. This talk will focus on interdependent considerat...
Saraju P. Mohanty
FLAIRS
2004
13 years 9 months ago
Highway Vehicle Classification by Probabilistic Neural Networks
The Federal Highway Administration (FHWA) Office of Highway Planning requires states to furnish vehicle classification data as part of the Highway Performance Monitoring Systems (...
Valerian Kwigizile, Majura F. Selekwa, Renatus N. ...
MTDT
2003
IEEE
164views Hardware» more  MTDT 2003»
14 years 25 days ago
Applying Defect-Based Test to Embedded Memories in a COT Model
ct Defect-based testing for digital logic concentrates primarily on methods of test application, including for example at-speed structural tests and IDDQ testing. In contrast, defe...
Robert C. Aitken
DAC
2009
ACM
14 years 8 months ago
Computing bounds for fault tolerance using formal techniques
Continuously shrinking feature sizes result in an increasing susceptibility of circuits to transient faults, e.g. due to environmental radiation. Approaches to implement fault tol...
André Sülflow, Görschwin Fey, Rol...