28 search results - page 1 / 6 » Design Issues and Tradeoffs for Write Buffers |
HPCA
1997
IEEE
13 years 11 months ago
1997
IEEE
Processors with write-through caches typically require a write buffer to hide the write latency to the next level of memory hierarchy and to reduce write traffic. A write buffer ...
ISCA
1994
IEEE
13 years 11 months ago
1994
IEEE
Wepresentaunijiedapp?'each to assess thet7adeoff of architecture techniques that affect mean memory access time. The architectural features we consider inciude cache hit Tati...
IWNAS
2006
IEEE
14 years 26 days ago
2006
IEEE
RDMA reduces network latency by eliminating unnecessary copies from network interface cards to application buffers, but how to reduce memory registration cost is a challenge. Prev...
CCGRID
2009
IEEE
14 years 1 months ago
2009
IEEE
In a cluster of multiple processors or cpu-cores, many processes may run on each compute node. Each process tends to issue contiguous I/O requests for snapshot, checkpointing or s...
ASPLOS
1991
ACM
13 years 10 months ago
1991
ACM
The memory consistency model supported by a multiprocessor architecture determines the amount of buffering and pipelining that may be used to hide or reduce the latency of memory ...