A Unified Architectural Tradeoff Methodology

Wepresentaunijiedapp?'each to assess thet7adeoff of architecture techniques that affect mean memory access time. The architectural features we consider inciude cache hit Tatio, processo7 stalling featuTes, line size, memo7y cycle time, the ezternal data bus width of aprocessor, pipeiined memory sysiem, and read bypassing write buffers. We demonstrate how each of these feaiwes can be traded off to achieve the desired performance. Thepe?'fo?'mance of an a7chitectu7efeatureis quantified in terms of cache hit ratio based on the equivalence of mean memory delay time. This paper investigates the implication of architectural tradeoffs on the pin count, memory system design, and onchip cache area for microprocessor systems.

• Type: Conference
• Year: 1994
• Where: ISCA
• Authors: Chung-Ho Chen, Arun K. Somani
• Keywords: Cache Hit, Hardware, ISCA 1994, Mean Memory, Mean Memory Access