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VLSID
2005
IEEE
158views VLSI» more  VLSID 2005»
14 years 8 months ago
Algorithmic Implementation of Low-Power High Performance FIR Filtering IP Cores
This paper presents two schemes for the implementation of high performance and low power FIR filtering Intellectual Property (IP) cores. Low power is achieved through the utilizat...
C. H. Wang, Ahmet T. Erdogan, Tughrul Arslan
SLIP
2003
ACM
14 years 27 days ago
A hierarchical three-way interconnect architecture for hexagonal processors
The problem of interconnect architecture arises when an array of processors needs to be integrated on one chip. With the deep sub-micron technology, devices become cheap while wir...
Feng Zhou, Esther Y. Cheng, Bo Yao, Chung-Kuan Che...
DAC
2007
ACM
14 years 8 months ago
High Performance and Low Power Electronics on Flexible Substrate
We propose a design and optimization methodology for high performance and ultra low power digital applications on flexible substrate using Low Temperature Polycrystalline Silicon ...
Jing Li, Kunhyuk Kang, Aditya Bansal, Kaushik Roy
TPDS
2008
140views more  TPDS 2008»
13 years 7 months ago
High-Performance Resource Allocation and Request Redirection Algorithms for Web Clusters
Abstract-- With increasing richness in features such as personalization of content, web applications are becoming more complex and hence compute intensive. Traditional approaches t...
Supranamaya Ranjan, Edward W. Knightly
HPCA
2006
IEEE
14 years 8 months ago
High performance file I/O for the Blue Gene/L supercomputer
Parallel I/O plays a crucial role for most data-intensive applications running on massively parallel systems like Blue Gene/L that provides the promise of delivering enormous comp...
Hao Yu, Ramendra K. Sahoo, C. Howson, G. Almasi, J...