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» Design Patterns for Reconfigurable Computing
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ERSA
2006
91views Hardware» more  ERSA 2006»
13 years 10 months ago
Intrinsic Embedded Hardware Evolution of Block-based Neural Networks
- An intrinsic embedded online evolution system has been designed using Block-based neural networks and implemented on Xilinx VirtexIIPro FPGAs. The designed network can dynamicall...
Saumil Merchant, Gregory D. Peterson, Seong Kong
ESTIMEDIA
2007
Springer
14 years 20 days ago
Still Image Processing on Coarse-Grained Reconfigurable Array Architectures
Due to the increasing demands on efficiency, performance and flexibility reconfigurable computational architectures are very promising candidates in embedded systems design. Recent...
Matthias Hartmann, Vasileios (Vassilis) Pantazis, ...
IPPS
2006
IEEE
14 years 2 months ago
Reconfigurable communications for image processing applications
: This work tries to reuse programmable communication resources like a Network-on-Chip (NoC) in the acceleration of image applications. We show a mathematical model for the computa...
André Borin Soares, Luigi Carro, Altamiro A...
MIDDLEWARE
2007
Springer
14 years 2 months ago
The case for aspect-oriented reflective middleware
The emergence of applications domains such as pervasive and autonomic computing has increased the need for customisation and dynamic adaptation of both distributed systems, and th...
Paul Grace, Eddy Truyen, Bert Lagaisse, Wouter Joo...
DAC
2004
ACM
14 years 15 days ago
An SoC design methodology using FPGAs and embedded microprocessors
In System on Chip (SoC) design, growing design complexity has esigners to start designs at higher abstraction levels. This paper proposes an SoC design methodology that makes full...
Nobuyuki Ohba, Kohji Takano