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HOTNETS
2010
13 years 3 months ago
Packet re-cycling: eliminating packet losses due to network failures
This paper presents Packet Re-cycling (PR), a technique that takes advantage of cellular graph embeddings to reroute packets that would otherwise be dropped in case of link or nod...
Suksant Sae Lor, Raul Landa, Miguel Rio
COCO
2011
Springer
221views Algorithms» more  COCO 2011»
12 years 8 months ago
Non-uniform ACC Circuit Lower Bounds
The class ACC consists of circuit families with constant depth over unbounded fan-in AND, OR, NOT, and MODm gates, where m > 1 is an arbitrary constant. We prove: • NTIME[2n ...
Ryan Williams
FPL
2009
Springer
117views Hardware» more  FPL 2009»
14 years 1 months ago
Data parallel FPGA workloads: Software versus hardware
Commercial soft processors are unable to effectively exploit the data parallelism present in many embedded systems workloads, requiring FPGA designers to exploit it (laboriously) ...
Peter Yiannacouras, J. Gregory Steffan, Jonathan R...
ISCA
2000
IEEE
103views Hardware» more  ISCA 2000»
14 years 1 months ago
Piranha: a scalable architecture based on single-chip multiprocessing
The microprocessor industry is currently struggling with higher development costs and longer design times that arise from exceedingly complex processors that are pushing the limit...
Luiz André Barroso, Kourosh Gharachorloo, R...
RTAS
1997
IEEE
14 years 25 days ago
Scalable Hardware Priority Queue Architectures for High-Speed Packet Switches
ÐWith effective packet-scheduling mechanisms, modern integrated networks can support the diverse quality-of-service requirements of emerging applications. However, arbitrating bet...
Sung-Whan Moon, Kang G. Shin, Jennifer Rexford