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» Design Principles for Combiners with Memory
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CODES
2008
IEEE
14 years 3 months ago
Static analysis of processor stall cycle aggregation
Processor Idle Cycle Aggregation (PICA) is a promising approach for low power execution of processors, in which small memory stalls are aggregated to create a large one, and the p...
Jongeun Lee, Aviral Shrivastava
BROADNETS
2006
IEEE
14 years 2 months ago
SeeMote: In-Situ Visualization and Logging Device for Wireless Sensor Networks
In this paper we address three challenges that are present when building and analyzing wireless sensor networks (WSN) as part of ubiquitous computing environment: the need for an ...
Leo Selavo, Gang Zhou, John A. Stankovic
ISCA
2005
IEEE
181views Hardware» more  ISCA 2005»
14 years 2 months ago
Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors
With the ability to place large numbers of transistors on a single silicon chip, manufacturers have begun developing chip multiprocessors (CMPs) containing multiple processor core...
Evan Speight, Hazim Shafi, Lixin Zhang, Ramakrishn...
WSNA
2003
ACM
14 years 1 months ago
Analyzing and modeling encryption overhead for sensor network nodes
Recent research in sensor networks has raised security issues for small embedded devices. Security concerns are motivated by the deployment of a large number of sensory devices in...
Prasanth Ganesan, Ramnath Venugopalan, Pushkin Ped...
CCS
2008
ACM
13 years 10 months ago
Code injection attacks on harvard-architecture devices
Harvard architecture CPU design is common in the embedded world. Examples of Harvard-based architecture devices are the Mica family of wireless sensors. Mica motes have limited me...
Aurélien Francillon, Claude Castelluccia