605 search results - page 25 / 121 » Design Principles for Combiners with Memory |
VLSID
2003
IEEE
14 years 9 months ago
2003
IEEE
Exploitation of silicon capacity will require improvements in design productivity and more scalable system paradigms. Asynchronous message passing networks on chip (NOC) have been...
HPCA
1997
IEEE
14 years 26 days ago
1997
IEEE
Processors with write-through caches typically require a write buffer to hide the write latency to the next level of memory hierarchy and to reduce write traffic. A write buffer ...
TROB
2010
13 years 7 months ago
2010
—A novel approach toward construction of robots is based on a concentric combination of precurved elastic tubes. By rotation and extension of the tubes with respect to each other...
HPCA
2012
IEEE
12 years 4 months ago
2012
IEEE
Recent research on memory disaggregation introduces a new architectural building block—the memory blade—as a cost-effective approach for memory capacity expansion and sharing ...
AUTOMATICA
2007
13 years 8 months ago
2007
The certainty equivalence approach to adaptive control is commonly used with two types of identifiers: passivity-based identifiers and swapping identifiers. The “passive” (...