Sciweavers

605 search results - page 39 / 121
» Design Principles for Combiners with Memory
Sort
View
IEEEPACT
2003
IEEE
14 years 1 months ago
Using Software Logging to Support Multi-Version Buffering in Thread-Level Speculation
In Thread-Level Speculation (TLS), speculative tasks generate memory state that cannot simply be combined with the rest of the system because it is unsafe. One way to deal with th...
María Jesús Garzarán, Milos P...
ICES
2000
Springer
91views Hardware» more  ICES 2000»
14 years 8 days ago
Dynamic Optimisation of Non-linear Feed Forward Circuits
Abstract. An evolutionary algorithm is used to evolve a digital circuit which computes a simple hash function mapping a 16-bit address space into an 8-bit one. The target technolog...
Ernesto Damiani, Valentino Liberali, Andrea Tettam...
LCPC
2001
Springer
14 years 1 months ago
Bridging the Gap between Compilation and Synthesis in the DEFACTO System
Abstract. The DEFACTO project - a Design Environment For Adaptive Computing TechnOlogy - is a system that maps computations, expressed in high-level languages such as C, directly o...
Pedro C. Diniz, Mary W. Hall, Joonseok Park, Byoun...
PLDI
2010
ACM
14 years 1 months ago
Z-rays: divide arrays and conquer speed and flexibility
Arrays are the ubiquitous organization for indexed data. Throughout programming language evolution, implementations have laid out arrays contiguously in memory. This layout is pro...
Jennifer B. Sartor, Stephen M. Blackburn, Daniel F...
LCPC
2007
Springer
14 years 2 months ago
Revisiting SIMD Programming
Massively parallel SIMD array architectures are making their way into embedded processors. In these architectures, a number of identical processing elements having small private st...
Anton Lokhmotov, Benedict R. Gaster, Alan Mycroft,...