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GLVLSI
2005
IEEE
124views VLSI» more  GLVLSI 2005»
14 years 2 months ago
A first look at the interplay of code reordering and configurable caches
The instruction cache is a popular target for optimizations of microprocessor-based systems because of the cache’s high impact on system performance and power, and because of th...
Ann Gordon-Ross, Frank Vahid, Nikil Dutt
ISLPED
2010
ACM
202views Hardware» more  ISLPED 2010»
13 years 8 months ago
MODEST: a model for energy estimation under spatio-temporal variability
Estimation of static and dynamic energy of caches is critical for high-performance low-power designs. Commercial CAD tools performing energy estimation statically are not aware of...
Shrikanth Ganapathy, Ramon Canal, Antonio Gonz&aac...
ICS
2007
Tsinghua U.
14 years 2 months ago
Cooperative cache partitioning for chip multiprocessors
This paper presents Cooperative Cache Partitioning (CCP) to allocate cache resources among threads concurrently running on CMPs. Unlike cache partitioning schemes that use a singl...
Jichuan Chang, Gurindar S. Sohi
CHI
2003
ACM
14 years 9 months ago
The digital set-top box as a virtual channel provider
This research is based on the realization that the desktop computing paradigm is not appropriate for television, because it is adapted to fundamentally different user aspirations ...
Konstantinos Chorianopoulos
TVCG
2010
147views more  TVCG 2010»
13 years 7 months ago
Superquadric Glyphs for Symmetric Second-Order Tensors
—Symmetric second-order tensor fields play a central role in scientific and biomedical studies as well as in image analysis and feature-extraction methods. The utility of displ...
Thomas Schultz, Gordon L. Kindlmann