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» Design Recovery of a Two Level System
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RTCSA
2007
IEEE
14 years 1 months ago
An MPSoC Performance Estimation Framework Using Transaction Level Modeling
— To use the tremendous hardware resources available in next generation MultiProcessor Systems-on-Chip (MPSoC) efficiently, rapid and accurate design space exploration (DSE) met...
Rabie Ben Atitallah, Smaïl Niar, Samy Meftali...
IJCSA
2008
100views more  IJCSA 2008»
13 years 7 months ago
A Smart Architecture for Low-Level Image Computing
This paper presents a comparison relating two different vision system architectures. The first one involves a smart sensor including analog processors allowing on-chip image proce...
A. Elouardi, Samir Bouaziz, Antoine Dupret, Lionel...
TR
2010
131views Hardware» more  TR 2010»
13 years 2 months ago
A Memetic Algorithm for Multi-Level Redundancy Allocation
Redundancy allocation problems (RAPs) have attracted much attention for the past thirty years due to its wide applications in improving the reliability of various engineering syste...
Zai Wang, Ke Tang, Xin Yao
ICVGIP
2004
13 years 9 months ago
Use of Linear Diffusion in Depth Estimation Based on Defocus Cue
Diffusion has been used extensively in computer vision. Most common applications of diffusion have been in low level vision problems like segmentation and edge detection. In this ...
Vinay P. Namboodiri, Subhasis Chaudhuri
ISCAS
1999
IEEE
87views Hardware» more  ISCAS 1999»
13 years 12 months ago
Instruction level power model of microcontrollers
In the design of low power systems, it is important to analyze and optimize both the hardware and the software component of the system. To evaluate the software component of the s...
C. Chakrabarti, D. Gaitonde