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» Design Technology for Networked Reconfigurable FPGA Platform...
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139
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LCN
2002
IEEE
15 years 9 months ago
Design and Analysis of a Dynamically Reconfigurable Network Processor
The combination of high-performance processing power and flexibility found in network processors (NPs) has made them a good solution for today’s packet processing needs. Similar...
Ian A. Troxel, Alan D. George, Sarp Oral
ARC
2009
Springer
134views Hardware» more  ARC 2009»
15 years 8 months ago
A HyperTransport 3 Physical Layer Interface for FPGAs
Abstract. This paper presents the very first implementation of a HyperTransport 3 physical layer interface for Field Programmable Gate Arrays. HyperTransport is a low latency, high...
Heiner Litz, Holger Fröning, Ulrich Brün...
EH
2004
IEEE
163views Hardware» more  EH 2004»
15 years 7 months ago
Towards Evolvable Analog Artificial Neural Networks Controllers
This work deals with the design of analog circuits for Artificial Neural Networks (ANNs) controllers using an Evolvable Hardware (EHW) platform. ANNs are massively parallel system...
José Franco Machado do Amaral, Jorge Lu&iac...
FPGA
2004
ACM
174views FPGA» more  FPGA 2004»
15 years 9 months ago
A compiled accelerator for biological cell signaling simulations
The simulation of large systems of biochemical reactions is a key part of research into molecular signaling and information processing in biological cells. However, it can be impr...
John F. Keane, Christopher Bradley, Carl Ebeling
129
Voted
SIGSOFT
2001
ACM
16 years 4 months ago
A graph based architectural (Re)configuration language
For several different reasons, such as changes in the business or technological environment, the configuration of a system may need to evolve during execution. Support for such ev...
Michel Wermelinger, Antónia Lopes, Jos&eacu...