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ISCA
2008
IEEE
112views Hardware» more  ISCA 2008»
14 years 3 months ago
Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems
In a chip-multiprocessor (CMP) system, the DRAM system is shared among cores. In a shared DRAM system, requests from a thread can not only delay requests from other threads by cau...
Onur Mutlu, Thomas Moscibroda
WSC
2004
13 years 10 months ago
Investigation of Error Rates When Controlling Multiple Uninhabited Combat Aerial Vehicles
As systems become more and more complex the use of automation tools becomes more important. Although automation is introduced to reduce human workload, improve situational awarene...
Sasanka V. Prabhala, Jennie J. Gallimore
CEC
2008
IEEE
14 years 3 months ago
High-level synthesis with multi-objective genetic algorithm: A comparative encoding analysis
— The high-level synthesis process involves three interdependent and NP-complete optimization problems: (i) the operation scheduling, (ii) the resource allocation, and (iii) the ...
Christian Pilato, Daniele Loiacono, Fabrizio Ferra...
ISCA
2008
IEEE
150views Hardware» more  ISCA 2008»
14 years 3 months ago
Fetch-Criticality Reduction through Control Independence
Architectures that exploit control independence (CI) promise to remove in-order fetch bottlenecks, like branch mispredicts, instruction-cache misses and fetch unit stalls, from th...
Mayank Agarwal, Nitin Navale, Kshitiz Malik, Matth...
SC
2009
ACM
14 years 1 months ago
A framework for core-level modeling and design of reconfigurable computing algorithms
Reconfigurable computing (RC) is rapidly becoming a vital technology for many applications, from high-performance computing to embedded systems. The inherent advantages of custom-...
Gongyu Wang, Greg Stitt, Herman Lam, Alan D. Georg...