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» Design and Analysis of a Robust Pipelined Memory System
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VLSID
2003
IEEE
147views VLSI» more  VLSID 2003»
14 years 7 months ago
SoC Synthesis with Automatic Hardware Software Interface Generation
Design of efficient System-on-Chips (SoCs) require thorough application analysis to identify various compute intensive parts. These compute intensive parts can be mapped to hardwa...
Amarjeet Singh 0002, Amit Chhabra, Anup Gangwar, B...
OOPSLA
2009
Springer
14 years 2 months ago
Scalable nonblocking concurrent objects for mission critical code
The high degree of complexity and autonomy of future robotic space missions, such as Mars Science Laboratory (MSL), poses serious challenges in assuring their reliability and efï¬...
Damian Dechev, Bjarne Stroustrup
IEEEPACT
2006
IEEE
14 years 1 months ago
Communist, utilitarian, and capitalist cache policies on CMPs: caches as a shared resource
As chip multiprocessors (CMPs) become increasingly mainstream, architects have likewise become more interested in how best to share a cache hierarchy among multiple simultaneous t...
Lisa R. Hsu, Steven K. Reinhardt, Ravishankar R. I...
PADS
1999
ACM
13 years 11 months ago
Shock Resistant Time Warp
In an attempt to cope with time-varying workload, traditional adaptive Time Warp protocols are designed to react in response to performance changes by altering control parameter c...
Alois Ferscha, James Johnson
DAMON
2008
Springer
13 years 9 months ago
CAM conscious integrated answering of frequent elements and top-k queries over data streams
Frequent elements and top-k queries constitute an important class of queries for data stream analysis applications. Certain applications require answers for both frequent elements...
Sudipto Das, Divyakant Agrawal, Amr El Abbadi