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» Design and Analysis of a Robust Pipelined Memory System
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EH
2005
IEEE
127views Hardware» more  EH 2005»
14 years 1 months ago
On the Robustness Achievable with Stochastic Development Processes
Manufacturing processes are a key source of faults in complex hardware systems. Minimizing this impact of manufacturing uncertainties is one way towards achieving fault tolerant s...
Shivakumar Viswanathan, Jordan B. Pollack
HPCC
2005
Springer
14 years 1 months ago
Lazy Home-Based Protocol: Combining Homeless and Home-Based Distributed Shared Memory Protocols
Abstract. This paper presents our novel protocol design and implementation of an all-software page-based DSM system. The protocol combines the advantages of homeless and home-based...
Byung-Hyun Yu, Paul Werstein, Martin K. Purvis, St...
WMPI
2004
ACM
14 years 1 months ago
A low cost, multithreaded processing-in-memory system
This paper discusses die cost vs. performance tradeoffs for a PIM system that could serve as the memory system of a host processor. For an increase of less than twice the cost of ...
Jay B. Brockman, Shyamkumar Thoziyoor, Shannon K. ...
ASPDAC
2007
ACM
107views Hardware» more  ASPDAC 2007»
13 years 11 months ago
Advanced tools for simulation and design of oscillators/PLLs
We present a robust, automated oscillator macromodeling technique for extracting comprehensive phase and amplitude macromodels from oscillators' SPICE circuit descriptions. Th...
Xiaolue Lai, Jaijeet S. Roychowdhury
RSP
2008
IEEE
182views Control Systems» more  RSP 2008»
14 years 2 months ago
From Application to ASIP-based FPGA Prototype: a Case Study on Turbo Decoding
ASIP-based implementations constitute a key trend in SoC design enabling optimal tradeoffs between performance and flexibility. This paper details a case study of an ASIP-based im...
Olivier Muller, Amer Baghdadi, Michel Jéz&e...