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» Design and Analysis of a Robust Pipelined Memory System
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ECRTS
2010
IEEE
13 years 7 months ago
The Demand Bound Function Interface of Distributed Sporadic Pipelines of Tasks Scheduled by EDF
—In distributed real-time embedded systems (DRE), it is common to model an application as a set of task chains. Each chain is activated cyclically and must complete before an end...
Nicola Serreli, Giuseppe Lipari, Enrico Bini
MICRO
2008
IEEE
103views Hardware» more  MICRO 2008»
14 years 1 months ago
Testudo: Heavyweight security analysis via statistical sampling
Heavyweight security analysis systems, such as taint analysis and dynamic type checking, are powerful technologies used to detect security vulnerabilities and software bugs. Tradi...
Joseph L. Greathouse, Ilya Wagner, David A. Ramos,...
ISCA
2002
IEEE
82views Hardware» more  ISCA 2002»
14 years 13 days ago
Increasing Processor Performance by Implementing Deeper Pipelines
One architectural method for increasing processor performance involves increasing the frequency by implementing deeper pipelines. This paper will explore the relationship between ...
Eric Sprangle, Doug Carmean
ASPDAC
2006
ACM
178views Hardware» more  ASPDAC 2006»
14 years 1 months ago
Hardware architecture design of an H.264/AVC video codec
Abstract—H.264/AVC is the latest video coding standard. It significantly outperforms the previous video coding standards, but the extraordinary huge computation complexity and m...
Tung-Chien Chen, Chung-Jr Lian, Liang-Gee Chen
PODC
1990
ACM
13 years 11 months ago
Sharing Memory Robustly in Message-Passing Systems
Emulators that translate algorithms from the shared-memory model to two different message-passing models are presented. Both are achieved by implementing a wait-free, atomic, singl...
Hagit Attiya, Amotz Bar-Noy, Danny Dolev