Sciweavers

1084 search results - page 118 / 217
» Design and Evaluation of a Selective Compressed Memory Syste...
Sort
View
ICPP
2005
IEEE
15 years 10 months ago
Exploring Processor Design Options for Java-Based Middleware
Java-based middleware is a rapidly growing workload for high-end server processors, particularly Chip Multiprocessors (CMP). To help architects design future microprocessors to ru...
Martin Karlsson, Erik Hagersten, Kevin E. Moore, D...
MICRO
2010
IEEE
172views Hardware» more  MICRO 2010»
15 years 2 months ago
Architectural Support for Fair Reader-Writer Locking
Abstract--Many shared-memory parallel systems use lockbased synchronization mechanisms to provide mutual exclusion or reader-writer access to memory locations. Software locks are i...
Enrique Vallejo, Ramón Beivide, Adriá...
IRI
2007
IEEE
15 years 10 months ago
Natural Language Processing and e-Government: Extracting Reusable Crime Report Information
Crime reporting needs to be possible 24/7. Although 911 and tip-lines are the most publicized reporting mechanisms, several other options exist, ranging from inperson reporting to...
Alicia Iriberri, Gondy Leroy
CASES
2003
ACM
15 years 9 months ago
Frequent loop detection using efficient non-intrusive on-chip hardware
Dynamic software optimization methods are becoming increasingly popular for improving software performance and power. The first step in dynamic optimization consists of detecting ...
Ann Gordon-Ross, Frank Vahid
ASPLOS
2012
ACM
14 years 6 days ago
Scalable address spaces using RCU balanced trees
Software developers commonly exploit multicore processors by building multithreaded software in which all threads of an application share a single address space. This shared addre...
Austin T. Clements, M. Frans Kaashoek, Nickolai Ze...