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ISCA
1996
IEEE
99views Hardware» more  ISCA 1996»
15 years 8 months ago
High-Bandwidth Address Translation for Multiple-Issue Processors
In an effort to push the envelope of system performance, microprocessor designs are continually exploiting higher levels of instruction-level parallelism, resulting in increasing ...
Todd M. Austin, Gurindar S. Sohi
CN
2007
114views more  CN 2007»
15 years 4 months ago
BiSNET: A biologically-inspired middleware architecture for self-managing wireless sensor networks
This paper describes BiSNET (Biologically-inspired architecture for Sensor NETworks), a middleware architecture that addresses several key issues in multi-modal wireless sensor ne...
Pruet Boonma, Junichi Suzuki
FCCM
2009
IEEE
115views VLSI» more  FCCM 2009»
15 years 8 months ago
Multi-Core Architecture on FPGA for Large Dictionary String Matching
FPGA has long been considered an attractive platform for high performance implementations of string matching. However, as the size of pattern dictionaries continues to grow, such ...
Qingbo Wang, Viktor K. Prasanna
SASP
2008
IEEE
164views Hardware» more  SASP 2008»
15 years 10 months ago
AMPLE: An Adaptive Multi-Performance Processor for Low-Energy Embedded Applications
This paper proposes an energy efficient processor which can be used as a design alternative for the dynamic voltage scaling (DVS) processors in embedded system design. The proces...
Tohru Ishihara, Seiichiro Yamaguchi, Yuriko Ishito...
FAST
2004
15 years 5 months ago
Tracefs: A File System to Trace Them All
File system traces have been used for years to analyze user behavior and system software behavior, leading to advances in file system and storage technologies. Existing traces, ho...
Akshat Aranya, Charles P. Wright, Erez Zadok