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HPCA
2008
IEEE
14 years 8 months ago
System level analysis of fast, per-core DVFS using on-chip switching regulators
Portable, embedded systems place ever-increasing demands on high-performance, low-power microprocessor design. Dynamic voltage and frequency scaling (DVFS) is a well-known techniq...
Wonyoung Kim, Meeta Sharma Gupta, Gu-Yeon Wei, Dav...
ICS
2007
Tsinghua U.
14 years 2 months ago
Representation-transparent matrix algorithms with scalable performance
Positive results from new object-oriented tools for scientific programming are reported. Using template classes, abstractions of matrix representations are available that subsume...
Peter Gottschling, David S. Wise, Michael D. Adams
HPCS
2006
IEEE
14 years 2 months ago
Toward a Software Infrastructure for the Cyclops-64 Cellular Architecture
This paper presents the initial design of the Cyclops-64 (C64) system software infrastructure and tools under development as a joint effort between IBM T.J. Watson Research Center...
Juan del Cuvillo, Weirong Zhu, Ziang Hu, Guang R. ...
CCGRID
2005
IEEE
14 years 2 months ago
Efficient resource description and high quality selection for virtual grids
Simple resource specification, resource selection, and effective binding are critical capabilities for Grid middleware. We the Virtual Grid, an abstraction for dynamic grid applic...
Yang-Suk Kee, D. Logothetis, Richard Y. Huang, Hen...
ANCS
2007
ACM
14 years 11 days ago
Ruler: high-speed packet matching and rewriting on NPUs
Programming specialized network processors (NPU) is inherently difficult. Unlike mainstream processors where architectural features such as out-of-order execution and caches hide ...
Tomas Hruby, Kees van Reeuwijk, Herbert Bos