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PPL
2008
185views more  PPL 2008»
13 years 7 months ago
On Design and Application Mapping of a Network-on-Chip(NoC) Architecture
As the number of integrated IP cores in the current System-on-Chips (SoCs) keeps increasing, communication requirements among cores can not be sufficiently satisfied using either ...
Jun Ho Bahn, Seung Eun Lee, Yoon Seok Yang, Jungso...
CVIU
2010
267views more  CVIU 2010»
13 years 5 months ago
Accelerated hardware video object segmentation: From foreground detection to connected components labelling
This paper demonstrates the use of a single-chip FPGA for the segmentation of moving objects in a video sequence. The system maintains highly accurate background models, and integ...
Kofi Appiah, Andrew Hunter, Patrick Dickinson, Hon...
AC
2008
Springer
13 years 7 months ago
Distributed Sparse Matrices for Very High Level Languages
Sparse matrices are first class objects in many VHLLs (very high level languages) used for scientific computing. They are a basic building block for various numerical and combinat...
John R. Gilbert, Steve Reinhardt, Viral Shah
IPPS
2008
IEEE
14 years 2 months ago
High performance MPEG-2 software decoder on the cell broadband engine
The Sony-Toshiba-IBM Cell Broadband Engine is a heterogeneous multicore architecture that consists of a traditional microprocessor (PPE) with eight SIMD coprocessing units (SPEs) ...
David A. Bader, Sulabh Patel
PPOPP
2003
ACM
14 years 1 months ago
Optimizing data aggregation for cluster-based internet services
Large-scale cluster-based Internet services often host partitioned datasets to provide incremental scalability. The aggregation of results produced from multiple partitions is a f...
Lingkun Chu, Hong Tang, Tao Yang, Kai Shen