Sciweavers

243 search results - page 30 / 49
» Design and Implementation of a CFAR Processor for Target Det...
Sort
View
ISCAS
2003
IEEE
144views Hardware» more  ISCAS 2003»
14 years 27 days ago
A flexible global readout architecture for an analogue SIMD vision chip
A new vision chip, SCAMP-2, has been developed in a 0.35µm CMOS technology. In this paper, the design of the chip is presented, with particular emphasis on its readout architectu...
Piotr Dudek
FPGA
2005
ACM
195views FPGA» more  FPGA 2005»
14 years 1 months ago
Sparse Matrix-Vector multiplication on FPGAs
Floating-point Sparse Matrix-Vector Multiplication (SpMXV) is a key computational kernel in scientific and engineering applications. The poor data locality of sparse matrices sig...
Ling Zhuo, Viktor K. Prasanna
MOBISYS
2007
ACM
14 years 7 months ago
SmartSiren: virus detection and alert for smartphones
Smartphones have recently become increasingly popular because they provide "all-in-one" convenience by integrating traditional mobile phones with handheld computing devi...
Jerry Cheng, Starsky H. Y. Wong, Hao Yang, Songwu ...
OOPSLA
2010
Springer
13 years 6 months ago
Supporting dynamic, third-party code customizations in JavaScript using aspects
Web sites and web browsers have recently evolved into platforms on top of which entire applications are delivered dynamically, mostly as JavaScript source code. This delivery form...
Benjamin S. Lerner, Herman Venter, Dan Grossman
VALUETOOLS
2006
ACM
167views Hardware» more  VALUETOOLS 2006»
14 years 1 months ago
Detailed cache simulation for detecting bottleneck, miss reason and optimization potentialities
Cache locality optimization is an efficient way for reducing the idle time of modern processors in waiting for needed data. This kind of optimization can be achieved either on the...
Jie Tao, Wolfgang Karl