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ACSC
2003
IEEE
14 years 28 days ago
FITS - A Fault Injection Architecture for Time-Triggered Systems
Time-triggered systems require a very high degree of temporal accuracy at critical stages during run time. While many software fault injection environments exist today, none of th...
René Hexel
TOG
2012
298views Communications» more  TOG 2012»
11 years 10 months ago
Tensor displays: compressive light field synthesis using multilayer displays with directional backlighting
We introduce tensor displays: a family of compressive light field displays comprising all architectures employing a stack of timemultiplexed, light-attenuating layers illuminated...
Gordon Wetzstein, Douglas Lanman, Matthew Hirsch, ...
GLVLSI
2005
IEEE
132views VLSI» more  GLVLSI 2005»
14 years 1 months ago
FPGA implementation of a modular and pipelined WF scheduler for high speed OC192 networks
In this paper we propose an FPGA implementation of a multi protocol Weighted Fair (WF) queuing algorithm able to handle variable length packets targeted for Packet Over Sonet (POS...
Abdallah Merhebi, Otmane Aït Mohamed
AAAIDEA
2005
IEEE
14 years 1 months ago
Design and Evaluation of Diffserv Functionalities in the MPLS Edge Router Architecture
—Differentiated Service (DiffServ) in combination with Multi-Protocol Label Switching (MPLS) is a promising technology in converting the best-effort Internet into a QoS-capable n...
Wei-Chu Lai, Kuo-Ching Wu, Ting-Chao Hou
IPPS
2003
IEEE
14 years 27 days ago
So Many States, So Little Time: Verifying Memory Coherence in the Cray X1
This paper investigates a complexity-effective technique for verifying a highly distributed directory-based cache coherence protocol. We develop a novel approach called “witnes...
Dennis Abts, Steve Scott, David J. Lilja