1224 search results - page 106 / 245 » Design and Implementation of a Practical Parallel Delaunay A... |
103
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ASPDAC
2006
ACM
15 years 10 months ago
2006
ACM
— We have designed and implemented the LDPC decoder chip with memory-reduction method to achieve high-throughput and practical chip size. The decoder decodes (3,6)-2304bit regula...
122
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IPPS
2006
IEEE
15 years 10 months ago
2006
IEEE
MPI middleware glues together the components necessary for execution. Almost all implementations have a communication component also called a message progression layer that progre...
249
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ICFP
2009
ACM
16 years 5 months ago
2009
ACM
Purely functional programs should run well on parallel hardware because of the absence of side effects, but it has proved hard to realise this potential in practice. Plenty of pap...
124
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LSSC
2005
Springer
15 years 10 months ago
2005
Springer
A new parallel algorithm for signal processing and a parallel systolic architecture of a robust constant false alarm rate (CFAR) processor with post-detection integration and adap...
177
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VG
2003
15 years 5 months ago
2003
The shear-warp volume rendering algorithm is one of the fastest algorithms for volume rendering, but it achieves this rendering speed only by sacrificing interpolation between th...