164 search results - page 22 / 33 » Design and Implementation of the Memory Scheduler for the PC... |
149
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DATE
2009
IEEE
16 years 24 days ago
2009
IEEE
Abstract—High computational effort in modern image processing applications like medical imaging or high-resolution video processing often demands for massively parallel special p...
204
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JMLR
2010
15 years 25 days ago
2010
The FastInf C++ library is designed to perform memory and time efficient approximate inference in large-scale discrete undirected graphical models. The focus of the library is pro...
125
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EPIA
1999
Springer
15 years 10 months ago
1999
Springer
YapOr is an or-parallel system that extends the Yap Prolog system to exploit implicit or-parallelism in Prolog programs. It is based on the environment copying model, as first imp...
176
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RTSS
2008
IEEE
16 years 13 days ago
2008
IEEE
This paper presents the design of user-level scheduling hierarchies in the Composite component-based system. The motivation for this is centered around the design of a system that...
154
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ARCS
2005
Springer
15 years 11 months ago
2005
Springer
Abstract. The SoC (System-on-Chip) technology is used in small and flexible consumer electronic devices. SoCs include one or more microcontroller, memory, programmable logic, and ...