164 search results - page 6 / 33 » Design and Implementation of the Memory Scheduler for the PC... |
ICC
2008
IEEE
14 years 3 months ago
2008
IEEE
— Designing switching architectures for network routers and switches needs to consider limits imposed by the electronic technology, like small bandwidth×distance factors, power ...
ISCA
2012
IEEE
11 years 11 months ago
2012
IEEE
When multiple processor (CPU) cores and a GPU integrated together on the same chip share the off-chip main memory, requests from the GPU can heavily interfere with requests from t...
IEEEPACT
2003
IEEE
14 years 2 months ago
2003
IEEE
We investigate the implementation of IP look-up for core routers using multiple microengines and a tailored memory hierarchy. The main architectural concerns are limiting the numb...
INFOCOM
2002
IEEE
14 years 1 months ago
2002
IEEE
Abstract— Continuing growth in optical link speeds places increasing demands on the performance of Internet routers, while deployment of embedded and distributed network services...
LCN
2005
IEEE
14 years 2 months ago
2005
IEEE
— The problem of achieving fairness in the allocation of the bandwidth resource on a link shared by multiple flows of traffic has been extensively researched over the last deca...