Sciweavers

862 search results - page 25 / 173
» Design and Implementation of the TRIPS Primary Memory System
Sort
View
ISCAS
1994
IEEE
138views Hardware» more  ISCAS 1994»
14 years 17 days ago
High-Throughput Data Compressor Designs Using Content Addressable Memory
This paper presents a novel VLSI architecture for high-speed data compressor designs which implement the well-known LZ77 algorithm. The architecture mainly consists of three units...
Ren-Yang Yang, Chen-Yi Lee
ASPDAC
2012
ACM
253views Hardware» more  ASPDAC 2012»
12 years 4 months ago
An integrated and automated memory optimization flow for FPGA behavioral synthesis
Behavioral synthesis tools have made significant progress in compiling high-level programs into register-transfer level (RTL) specifications. But manually rewriting code is still ...
Yuxin Wang, Peng Zhang, Xu Cheng, Jason Cong
USENIX
1993
13 years 9 months ago
A Library Implementation of POSIX Threads under UNIX
Recently, there has been an effort to specify an IEEE standard for portable operating systems for open systems, called POSIX. One part of it, the POSIX 1003.4a threads extension (...
Frank Mueller
ISCA
1994
IEEE
123views Hardware» more  ISCA 1994»
14 years 17 days ago
Software-Extended Coherent Shared Memory: Performance and Cost
This paper evaluates the tradeoffs involved in the design of the software-extended memory system of Alewife, a multiprocessor architecturethat implements coherentsharedmemorythrou...
David Chaiken, Anant Agarwal
ICPPW
2006
IEEE
14 years 2 months ago
Model-Based OpenMP Implementation of a 3D Facial Pose Tracking System
Abstract— Most image processing applications are characterized by computation-intensive operations, and high memory and performance requirements. Parallelized implementation on s...
Sankalita Saha, Chung-Ching Shen, Chia-Jui Hsu, Ga...