862 search results - page 45 / 173 » Design and Implementation of the TRIPS Primary Memory System |
ISCA
2006
IEEE
13 years 8 months ago
2006
IEEE
: Tiled architectures, such as RAW, SmartMemories, TRIPS, and WaveScalar, promise to address several issues facing conventional processors, including complexity, wire-delay, and pe...
IEEEPACT
2003
IEEE
14 years 1 months ago
2003
IEEE
In Thread-Level Speculation (TLS), speculative tasks generate memory state that cannot simply be combined with the rest of the system because it is unsafe. One way to deal with th...
ASPLOS
2000
ACM
14 years 26 days ago
2000
ACM
This paper describes the architecture and implementation of the AlphaServer GS320, a cache-coherent non-uniform memory access multiprocessor developed at Compaq. The AlphaServer G...
ICANN
2005
Springer
14 years 2 months ago
2005
Springer
Many approaches have emerged in the attempt to explain the memory process. One of which is the Theory of Neuronal Group Selection (TNGS), proposed by Edelman [1]. In the present wo...
OSDI
1996
ACM
13 years 9 months ago
1996
ACM
Non-blocking synchronization has significant advantages over blocking synchronization: however, it has not been used to a significant degree in practice. We designed and implement...