862 search results - page 7 / 173 » Design and Implementation of the TRIPS Primary Memory System |
ISCA
2006
IEEE
13 years 7 months ago
2006
IEEE
The assumption of maximum parallelism support for the successful realization of scalable quantum computers has led to homogeneous, "sea-of-qubits" architectures. The res...
LCTRTS
2010
Springer
13 years 5 months ago
2010
Springer
In this paper, we propose a hybrid-level flash translation layer (FTL) called RNFTL (Reuse-Aware NFTL) to improve the endurance and space utilization of NAND flash memory. Our bas...
ISCA
2009
IEEE
14 years 2 months ago
2009
IEEE
Analysis of technology and application trends reveals a growing imbalance in the peak compute-to-memory-capacity ratio for future servers. At the same time, the fraction contribut...
TC
1998
13 years 7 months ago
1998
—This paper describes the methods used to formulate and validate the memory subsystem of the cache-coherent Sun Scalable emory MultiProcessor (S3.mp) at three levels of abstracti...
VLDB
1999
ACM
13 years 11 months ago
1999
ACM
As random access memory gets cheaper, it becomes increasingly affordable to build computers with large main memories. We consider decision support workloads within the context of...