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» Design and evaluation of an auto-memoization processor
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MICRO
2006
IEEE
127views Hardware» more  MICRO 2006»
14 years 1 months ago
A Predictive Performance Model for Superscalar Processors
Designing and optimizing high performance microprocessors is an increasingly difficult task due to the size and complexity of the processor design space, high cost of detailed si...
P. J. Joseph, Kapil Vaswani, Matthew J. Thazhuthav...
IPPS
1996
IEEE
13 years 12 months ago
An Optical Interconnect Model for k-ary n-cube Wormhole Networks
This paper presents an optical interconnect model for kary n-cube network topologies based on free-space analysis. This model integrates relevant parameters inherent to optics wit...
Mongkol Raksapatcharawong, Timothy Mark Pinkston
EUROPAR
1999
Springer
14 years 6 hour ago
An Evaluation of High Performance Fortran Compilers Using the HPFBench Benchmark Suite
Abstract. The High Performance Fortran (HPF) benchmark suite HPFBench was designed for evaluating the HPF language and compilers on scalable architectures. The functionality of the...
Guohua Jin, Y. Charlie Hu
CHES
2009
Springer
150views Cryptology» more  CHES 2009»
14 years 2 months ago
A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions
Power-based side channel attacks are a significant security risk, especially for embedded applications. To improve the security of such devices, protected logic styles have been p...
Francesco Regazzoni, Alessandro Cevrero, Fran&cced...
GRID
2004
Springer
14 years 1 months ago
Design, Implementation and Performance Evaluation of GridRPC Programming Middleware for a Large-Scale Computational Grid
This paper reports on the design, implementation and performance evaluation of a suite of GridRPC programming middleware called Ninf-G Version 2 (Ninf-G2). NinfG2 is a reference i...
Yoshio Tanaka, Hiroshi Takemiya, Hidemoto Nakada, ...