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» Design and implementation of JPEG encoder IP core
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IEEEARES
2008
IEEE
14 years 1 months ago
Design of an FDB based Intra-domain Packet Traceback System
In this paper, we propose an FDB based intra-Domain Traceback System (FDB-DTS), which is a hybrid traceback system composed of packet digesting boxes and an iterative query engine...
Hiroaki Hazeyama, Yoshihide Matsumoto, Youki Kadob...
ENGL
2008
100views more  ENGL 2008»
13 years 7 months ago
HIDE+: A Logic Based Hardware Development Environment
With the advent of System-On-Chip (SOC) technology, there is a pressing need to enhance the quality of ools available and increase the level of abstraction at which hardware is des...
Abdsamad Benkrid, Khaled Benkrid
GLVLSI
2002
IEEE
106views VLSI» more  GLVLSI 2002»
14 years 10 days ago
A low power direct digital frequency synthesizer with 60 dBc spectral purity
We present a low-power sine-output Direct Digital Frequency Synthesizer (DDFS) realized in 0.18 µm CMOS that achieves 60 dBc spectral purity from DC to the Nyquist frequency. No ...
J. M. Pierre Langlois, Dhamin Al-Khalili
FPGA
2008
ACM
136views FPGA» more  FPGA 2008»
13 years 9 months ago
HybridOS: runtime support for reconfigurable accelerators
We present HybridOS, a set of operating system extensions for supporting fine-grained reconfigurable accelerators integrated with general-purpose computing platforms. HybridOS spe...
John H. Kelm, Steven S. Lumetta
SIGCOMM
2009
ACM
14 years 1 months ago
Optimizing the BSD routing system for parallel processing
The routing architecture of the original 4.4BSD [3] kernel has been deployed successfully without major design modification for over 15 years. In the unified routing architectur...
Qing Li, Kip Macy